Maximum Throughput Logic Synthesis for Stateful Logic: A Case Study

This paper investigates the design of deeply pipelined synchronous circuits with stateful logic, which can be implemented with several recently suggested emerging device technologies. Stateful logic is well suited for high-throughput processing because each gate combines logic and memory functionality. The downside of the high throughput computation is that all logic paths must have equal length. Using advanced logic synthesis techniques buffering needed to balance the path length is shown to result in an average overhead of 3x in gate count when mapped to several target libraries. Such high overhead of stateful logic may be still justified given an average 7.5x improvement in throughput per gate. Categories and Subject Descriptor B.5 [Register-transfer-level implementation]: Design Aids Automatic synthesis General Terms Algorithms, Design, Performance